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The library files from the same vendor are grouped in their separate directories. The default location where to put the library files is the vlib folder inside the Riviera-PRO main installation directory. You can either copy them to this folder or put them in any other convenient location.
Once the libraries have been extracted from the archive file and copied to their destination folder, e. Preferably you should map your libraries as global so that they can be accessed by any design from any location. You may open this file in the read mode to visually make sure all libraries are listed. Once the vendor libraries have been registered or mapped you can start compiling your design files that reference those libraries.
Note, that in case of Verilog you also need to point to the vendor libraries. When done, click on OK to close this dialog window. In case of VHDL no library pointing is necessary, since the libraries are being explicitly referenced in the library clause inside the source file. Application Notes. Post Simulation Debug is an advanced feature that allows users to observe the simulation results after the simulation has been finished.
In large designs where multiple signals must be observed during simulation, keeping them in one waveform window is inconvenient: since all signals cannot fit in one window, frequent scrolling is required to get to the desired waveform data.
The Compare Waveforms option compares waveforms displayed in the Waveform window with pattern waveforms from a specific waveform file. The Memory Viewer is a debugging tool that has been designed to display memory objects defined in an active design. Plot window is a debugging tool that visually represents large arrays of data. It support four different plot types and enables HDL design and verification engineers to not only visualize large data sets but also visualize and analyze relations between any objects in their design with no additional programming required.
Image windows is a debugging tool that displays image stored in a memory-like simulation object Image or visualizes simulation object values by a color Color Map. FSM window is debugging tool that allows observing finite state machine operations.
This tool generates a transition graph of any simulation object and shows transitions among object states or signal values. Design and verification engineers who implemented assertions and covers in their project can observe their behavior during regular simulation and debugging in multiple windows. X-Trace helps you quickly identify the cause of unexpected values by reporting information on changes from valid to unknown, uninitialized, or user-defined values in the simulated model.
The Dataflow window is a powerful tool that allows designers to explore the connectivity of an active design and analyze dataflow among instances, concurrent statements, signals, nets, and registers during simulation.
The Classes window is a debugging tool that presents SystemVerilog classes in the form of a hierarchical tree view.
With incremental compilation, small change in one of many design sources does not require recompilation of the entire design. Compilers working in incremental mode can ignore not only files that were not changed, but also areas of larger files that were not modified. Library protection offers four security levels when compiled models are distributed in the form of library files without releasing their source code.
Using standard design source encryption is a much easier form of managing IP creation and delivery than any kind of binary file encryption. Library compatibility across different platforms enables more efficient work of teams working on the same projects, but equipped with different workstations.
One set of design libraries can be kept in a convenient location with easy access from all team members. The ability for the simulator to run at bit bus throughput application speeds and utilize extended memory. Transaction-Level Visual Debugging refers to advanced capability of the Waveform Viewer that enables representing simulation data at a higher level of abstraction. The Profiler identifies design units or code sections that put the greatest strain on the simulator.
This information is valuable for optimizing the simulation environment and improving performance. Due to the complexity of contemporary designs, there is a need for extensive testing of new products. Server Farm Manager SFM shifts the regression paradigm and provides not only simulation technology but also a tool for automatic management of thousands of parallel simulations.
Acceleration speeds up verification by co-simulating HDL code and portions of the design pushed into hardware mainly well tested blocks or IP blocks. Emulation allows in-hardware simulation and extensive debugging of large systems that will eventually work on different platform. Code Coverage is a debugging tool that aids the verification process. Specification of properties and their use in assertions and functional coverage is the essential element of designing modern systems and their verification algorithms.
Functional Coverage can provide information about the quality of the design verification process. Keysight SystemVue co-simulation interface reduces development time and effort by enabling continuous test verification through the system and hardware development process.
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